HD6432351 Datasheet, PDF (190/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

• RAS up mode
To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space
is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is
only performed if DRAM space is continuous. Figure 6-22 shows an example of the timing in
RAS up mode.
In the case of burst ROM space access, the RAS signal is not restored to the high level.
DRAM access
DRAM access
External space
access
T_p
T_r
T_c1
T_c2
T_c1
T_c2
T₁
T₂
ø
A₂₃ to A₀
CSn (RAS)
CAS, LCAS
D₁₅ to D₀
Note: n = 2 to 5
Figure 6-22 Example of Operation Timing in RAS Up Mode
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