HD6432351 Datasheet, PDF (165/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.3.5 Areas in Normal Mode
In normal mode, a 64-kbyte address space comprising part of area 0 is controlled. Area
partitioning is not performed in normal mode. In ROM-disabled expansion mode, the space
excluding the on-chip RAM and internal I/O registers is external space. In ROM-enabled
expansion mode* the space excluding the on-chip ROM*, on-chip RAM, and internal I/O registers
is external space. The on-chip RAM is enabled when the RAME bit in the system control register
(SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the
corresponding space becomes external space .
When external space is accessed, the CS0 signal can be output.
The basic bus interface or burst ROM interface can be selected.
Note: * Only applies to the H8S/2351.
145