HD6432351 Datasheet, PDF (782/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table A-5 Number of Cycles in Instruction Execution (cont)
Instruction
MOV
MOVFPE
MOVTPE
MULXS
MULXU
NEG
NOP
NOT
OR
ORC
POP
PUSH
ROTL
ROTR
Mnemonic
MOV.L ERs,@(d:32,ERd)
MOV.L ERs,@-ERd
MOV.L ERs,@aa:16
MOV.L ERs,@aa:32
MOVFPE @:aa:16,Rd
MOVTPE Rs,@:aa:16
MULXS.B Rs,Rd
MULXS.W Rs,ERd
MULXU.B Rs,Rd
MULXU.W Rs,ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
NOP
NOT.B Rd
NOT.W Rd
NOT.L ERd
OR.B #xx:8,Rd
OR.B Rs,Rd
OR.W #xx:16,Rd
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
ORC #xx:8,CCR
ORC #xx:8,EXR
POP.W Rn
POP.L ERn
PUSH.W Rn
PUSH.L ERn
ROTL.B Rd
ROTL.B #2,Rd
ROTL.W Rd
ROTL.W #2,Rd
ROTL.L ERd
ROTL.L #2,ERd
ROTR.B Rd
ROTR.B #2,Rd
ROTR.W Rd
ROTR.W #2,Rd
ROTR.L ERd
ROTR.L #2,ERd
Branch
Instruction Address
Fetch
Read
Stack Byte Data Word Data Internal
Operation Access Access Operation
I
J
K
L
M
N
5
2
2
2
1
3
2
4
2
Can not be used in the H8S/2350 Series
2
11
2
19
1
11
1
19
1
1
1
1
1
1
1
1
1
2
1
3
2
1
2
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
762