HD6432351 Datasheet, PDF (418/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

• 26 interrupt sources
 For channels 0 and 3, four compare match/input capture dual-function interrupts and one
overflow interrupt can be requested independently
 For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one
overflow interrupt, and one underflow interrupt can be requested independently
• Automatic transfer of register data
 Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer
controller (DTC) or DMA controller (DMAC) activation
• Programmable pulse generator (PPG) output trigger can be generated
 Channel 0 to 3 compare match/input capture signals can be used as PPG output trigger
• A/D converter conversion start trigger can be generated
 Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter
conversion start trigger
• Module stop mode can be set
 As the initial setting, TPU operation is halted. Register access is enabled by exiting module
stop mode.
Table 10-1 lists the functions of the TPU.
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