HD6432351 Datasheet, PDF (271/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

For details, see section 7.3.4, DMA Control Register (DMACR).
Figure 7-16 shows an example of the setting procedure for block transfer mode.
Block transfer
mode setting
Set DMABCRH
[1]
Set transfer source
and transfer destination [2]
addresses
Set number of transfers [3]
Set DMACR
[4]
Read DMABCRL
[5]
Set DMABCRL
[6]
Block transfer mode
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the block size in both ETCRAH and
ETCRAL. Set the number of transfers in
ETCRB.
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Set the BLKE bit to 1 to select block transfer
mode.
• Specify whether the transfer source or the
transfer destination is a block area with the
BLKDIR bit.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts to the CPU with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Figure 7-16 Example of Block Transfer Mode Setting Procedure
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