HD6432351 Datasheet, PDF (534/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. The NDR contents should not be altered during the interval from compare
match B to compare match A (the non-overlap margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next
data must be written before the next compare match B occurs.
Figure 11-11 shows the timing of this operation.
Compare match A
Compare match B
NDR
PODR
Write to NDR
Write to NDR
0 output 0/1 output
Write to NDR
Do not write ^here
to NDR here
0 output 0/1 output
Write to NDR
Do not write ^here
to NDR here
Figure 11-11 Non-Overlapping Operation and NDR Write Timing
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