HD6432351 Datasheet, PDF (692/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 20-3 MSTP Bits and Corresponding On-Chip Supporting Modules
Register
Bit
Module
MSTPCRH MSTP15 DMA controller (DMAC)
MSTP14 Data transfer controller (DTC)
MSTP13 16-bit timer pulse unit (TPU)
MSTP12 —
MSTP11 Programmable pulse generator (PPG)
MSTP10 D/A converter
MSTP9 A/D converter
MSTP8 —
MSTPCRL MSTP7 —
MSTP6 Serial communication interface (SCI) channel 1
MSTP5 Serial communication interface (SCI) channel 0
MSTP4 —
MSTP3 —
MSTP2 —
MSTP1 —
MSTP0 —
Note: Bits 12, 8, 7, and 4 to 0 can be read or written to, but do not affect operation.
20.5.2 Usage Notes
DMAC/DTC Module Stop: Depending on the operating status of the DMAC or DTC, the
MSTP15 and MSTP14 bits may not be set to 1. Setting of the DMAC or DTC module stop mode
should be carried out only when the respective module is not activated.
For details, refer to section 7, DMA Controller, and section 8, Data Transfer Controller.
On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in
module stop mode. Consequently, if module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC
activation source. Interrupts should therefore be disabled before entering module stop mode.
Writing to MSTPCR: MSTPCR should only be written to by the CPU.
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