HD6432351 Datasheet, PDF (143/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 6-1 Bus Controller Pins (cont)
Name
Upper column address strobe
Lower column strobe
Wait
Bus request
Bus request acknowledge
Bus request output
Symbol I/O
CAS Output
LCAS
WAIT
Output
Input
BREQ Input
BACK Output
BREQO Output
Function
2-CAS DRAM upper column address strobe
signal.
DRAM lower column address strobe signal.
Wait request signal when accessing
external 3-state access space.
Request signal that releases bus to
external device.
Acknowledge signal indicating that bus has
been released.
External bus request signal used when
internal bus master accesses external
space when external bus is released.
6.1.4 Register Configuration
Table 6-2 summarizes the registers of the bus controller.
Table 6-2 Bus Controller Registers
Name
Abbreviation R/W
Bus width control register
ABWCR
R/W
Access state control register ASTCR
R/W
Wait control register H
WCRH
R/W
Wait control register L
WCRL
R/W
Bus control register H
BCRH
R/W
Bus control register L
BCRL
R/W
Memory control register
MCR
R/W
DRAM control register
DRAMCR
R/W
Refresh timer/counter
RTCNT
R/W
Refresh time constant register RTCOR
R/W
Notes: 1. Lower 16 bits of the address.
2. Determined by the MCU operating mode.
Initial Value
Power-On
Reset
Manual
Reset
H'FF/H'00*² Retained
H'FF
Retained
H'FF
Retained
H'FF
Retained
H'D0
Retained
H'3C
Retained
H'00
Retained
H'00
Retained
H'00
Retained
H'FF
Retained
Address*¹
H'FED0
H'FED1
H'FED2
H'FED3
H'FED4
H'FED5
H'FED6
H'FED7
H'FED8
H'FED9
123