HD6432351 Datasheet, PDF (491/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin. After a match between TCNT and TGR, the compare match signal is not
generated until the TCNT input clock is generated.
Figure 10-36 shows output compare output timing.
ø
TCNT
input clock
TCNT
N
N+1
TGR
N
Compare
match signal
TIOC pin
Figure 10-36 Output Compare Output Timing
Input Capture Signal Timing: Figure 10-37 shows input capture signal timing.
ø
Input capture
input
Input capture
signal
TCNT
TGR
N
N+1
N+2
N
N+2
Figure 10-37 Input Capture Input Signal Timing
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