HD6432351 Datasheet, PDF (407/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Pins PF₂ to PF₀ are designated as bus control input/output pins (LCAS, WAIT, BREQO,
BACK, BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1
makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an
input port.
• Modes 3 and 7 [H8S/2351 only]
Setting a PFDDR bit to 1 makes the corresponding port F pin PF₆ to PF₀ an output port, or in
the case of pin PF₇, the ø output pin. Clearing the bit to 0 makes the pin an input port.
Port F Data Register (PFDR)
Bit
:
Initial value :
R/W
:
7
PF7DR
0
R/W
6
PF6DR
0
R/W
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
2
PF2DR
0
R/W
1
PF1DR
0
R/W
0
PF0DR
0
R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF₇ to PF₀).
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Port F Register (PORTF)
Bit
:
7
6
5
4
3
2
1
0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
Initial value : —*
—*
—*
—*
—*
—*
—*
—*
R/W
:
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port
F pins (PF₇ to PF₀) must always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin
states, as PFDDR and PFDR are initialized. PORTF retains its prior state after a manual reset, and
in software standby mode.
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