HD6432351 Datasheet, PDF (599/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to
perform receive operations in units of one character, you should select an external clock as the
clock source.
Data Transfer Operations:
• SCI initialization (clocked synchronous mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0,
then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared
to 0 before making the change using the following procedure. When the TE bit is cleared to 0,
the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not
change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Figure 13-15 shows a sample SCI initialization flowchart.
Start initialization
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
Clear TE and RE bits in SCR to 0
TE and RE, to 0.
[2] Set the data transfer format in SMR
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
and SCMR.
[1]
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
Set data transfer format in
SMR and SCMR
external clock is used.
[2]
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Set value in BRR
[3]
Also set the RIE, TIE, TEIE, and MPIE
Wait
bits.
Setting the TE and RE bits enables the
No
TxD and RxD pins to be used.
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR to 1, and _[4]
set RIE, TIE, TEIE, and MPIE bits
<Transfer start>
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
to 0 or set to 1 simultaneously.
Figure 13-15 Sample SCI Initialization Flowchart
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