HD6432351 Datasheet, PDF (12/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

7.5.9 Basic DMAC Bus Cycles...................................................................................... 255
7.5.10 DMAC Bus Cycles (Dual Address Mode) ........................................................... 256
7.5.11 DMAC Bus Cycles (Single Address Mode) ......................................................... 264
7.5.12 Write Data Buffer Function .................................................................................. 270
7.5.13 DMAC Multi-Channel Operation ......................................................................... 271
7.5.14 Relation Between External Bus Requests, Refresh Cycles, the DTC,
and the DMAC...................................................................................................... 273
7.5.15 NMI Interrupts and DMAC .................................................................................. 274
7.5.16 Forced Termination of DMAC Operation ............................................................ 275
7.5.17 Clearing Full Address Mode................................................................................. 276
7.6 Interrupts ............................................................................................................................ 277
7.7 Usage Notes ....................................................................................................................... 278
Section 8 Data Transfer Controller ............................................................................... 283
8.1 Overview............................................................................................................................ 283
8.1.1 Features ................................................................................................................. 283
8.1.2 Block Diagram...................................................................................................... 284
8.1.3 Register Configuration.......................................................................................... 285
8.2 Register Descriptions ......................................................................................................... 286
8.2.1 DTC Mode Register A (MRA) ............................................................................. 286
8.2.2 DTC Mode Register B (MRB).............................................................................. 288
8.2.3 DTC Source Address Register (SAR) .................................................................. 289
8.2.4 DTC Destination Address Register (DAR) .......................................................... 289
8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 289
8.2.6 DTC Transfer Count Register B (CRB)................................................................ 290
8.2.7 DTC Enable Registers (DTCER).......................................................................... 290
8.2.8 DTC Vector Register (DTVECR) ........................................................................ 291
8.2.9 Module Stop Control Register (MSTPCR)........................................................... 292
8.3 Operation............................................................................................................................ 293
8.3.1 Overview............................................................................................................... 293
8.3.2 Activation Sources................................................................................................ 295
8.3.3 DTC Vector Table ................................................................................................ 296
8.3.4 Location of Register Information in Address Space............................................. 299
8.3.5 Normal Mode........................................................................................................ 300
8.3.6 Repeat Mode ......................................................................................................... 301
8.3.7 Block Transfer Mode............................................................................................ 302
8.3.8 Chain Transfer ...................................................................................................... 304
8.3.9 Operation Timing.................................................................................................. 305
8.3.10 Number of DTC Execution States ........................................................................ 306
8.3.11 Procedures for Using DTC.................................................................................... 308
8.3.12 Examples of Use of the DTC................................................................................ 309
8.4 Interrupts ............................................................................................................................ 311
8.5 Usage Notes ....................................................................................................................... 312
vi