HD6432351 Datasheet, PDF (596/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

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Error processing
No
ORER= 1
Yes
Overrun error processing
No
FER= 1
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCR to 0
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 13-12 Sample Multiprocessor Serial Reception Flowchart (cont)
Figure 13-13 shows an example of SCI operation for multiprocessor format reception.
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