HD6432351 Datasheet, PDF (853/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

MAR1BH — Memory Address Register 1BH
MAR1BL — Memory Address Register 1BL
H'FEF8
H'FEFA
DMAC
DMAC
Bit
: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR1BH : — — — — — — — —
Initial value : 0 0 0 0 0 0 0 0 * * * * * * * *
Read/Write : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR1BL :
Initial value : * * * * * * * * * * * * * * * *
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
* : Undefined
In short address mode: Specifies transfer source/transfer destination address
In full address mode: Specifies transfer destination address
IOAR1B—I/O Address Register 1B
H'FEFC
DMAC
Bit
: _{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
IOAR1B :
Initial value : _{* * * * * * * * * * * * * * * *}
Read/Write : _{R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W}
* : Undefined
In short address mode: Specifies transfer source/transfer destination address
In full address mode: Not used
ETCR1B—Transfer Count Register 1B
H'FEFE
DMAC
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETCR1B :
Initial value : * * * * * * * * * * * * * * * *
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Sequential mode
and idle mode
Transfer counter
Repeat mode
Block transfer mode
Transfer number storage register
Transfer counter
Block transfer counter
Note: Not used in normal mode.
* : Undefined
833