HD6432351 Datasheet, PDF (150/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.2.4 Bus Control Register H (BCRH)
Bit
:
Initial value :
R/W
:
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
4
3
2
BRSTRM BRSTS1 BRSTS0 RMTS2
0
1
0
0
R/W R/W R/W R/W
1
RMTS1
0
R/W
0
RMTS0
0
R/W
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle
insertion, and the memory interface for areas 2 to 5 and area 0.
BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 7
ICIS1
0
1
Description
Idle cycle not inserted in case of successive external read cycles in different areas
Idle cycle inserted in case of successive external read cycles in different areas
(Initial value)
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed.
Bit 6
ICIS0
0
1
Description
Idle cycle not inserted in case of successive external read and external write cycles
Idle cycle inserted in case of successive external read and external write cycles
(Initial value)
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM
interface. In normal mode, the selection can be made from the entire external space.
Bit 5
BRSTRM
0
1
Description
Area 0 is basic bus interface
Area 0 is burst ROM interface
(Initial value)
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