HD6432351 Datasheet, PDF (409/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 9-24 Port F Pin Functions (cont)
Pin
PF₃/LWR
Selection Method and Pin Functions
The pin function is switched as shown below according to the operating mode
and bit PF3DDR.
Operating
Mode
Modes 1, 2, 4, 5, 6*
Modes 3 and 7*
PF3DDR
—
0
1
Pin function
LWR output pin
PF₃ input pin
PF₃ output pin
PF₂/LCAS/WAIT/ The pin function is switched as shown below according to the combination of
BREQO
the operating mode, and bits RMTS2 to RMTS0, LCASS, BREQOE, WAITE,
ABW5 to ABW2, and PF2DDR.
Operating
Mode
Modes 1, 2, 4, 5, 6*
Modes 3 and 7*
LCASS
0
1*
—
BREQOE
0
1
—
—
WAITE
0
1
—
—
—
PF2DDR
0
1
—
—
—
0
1
Pin function
PF₂
input
pin
PF₂
output
pin
WAIT BREQO LCAS
input output output
pin
pin
pin
PF₂
input
pin
PF₂
output
pin
Note: 1. Only in DRAM space 16-bit access in modes 4 to 6 when RMTS2 to
RMTS0 = B'001 to B'011.
PF₁/BACK
The pin function is switched as shown below according to the combination of
the operating mode, and bits BRLE and PF1DDR.
Operating
Mode
Modes 1, 2, 4, 5, 6*
Modes 3 and 7*
BRLE
0
1
—
PF1DDR
0
1
—
0
1
Pin function
PF₁
PF₁
BACK
PF₁
PF₁
input pin output pin output pin input pin output pin
Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351.
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