HD6432351 Datasheet, PDF (777/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table A-5 Number of Cycles in Instruction Execution (cont)
Instruction Mnemonic
Bcc
BHI d:16
BLS d:16
BCC d:16 (BHS d:16)
BCS d:16 (BLO d:16)
BNE d:16
BEQ d:16
BVC d:16
BVS d:16
BPL d:16
BMI d:16
BGE d:16
BLT d:16
BGT d:16
BLE d:16
BCLR
BCLR #xx:3,Rd
BCLR #xx:3,@ERd
BCLR #xx:3,@aa:8
BCLR #xx:3,@aa:16
BCLR #xx:3,@aa:32
BCLR Rn,Rd
BCLR Rn,@ERd
BCLR Rn,@aa:8
BCLR Rn,@aa:16
BCLR Rn,@aa:32
BIAND
BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
BILD
BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
BILD #xx:3,@aa:32
BIOR
BIOR #xx:8,Rd
BIOR #xx:8,@ERd
BIOR #xx:8,@aa:8
BIOR #xx:8,@aa:16
BIOR #xx:8,@aa:32
Instruction
Fetch
I
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
3
4
1
2
2
3
4
1
2
2
3
4
1
2
2
3
4
1
2
2
3
4
Branch
Address
Read
J
Stack Byte Data Word Data Internal
Operation Access Access Operation
K
L
M
N
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
757