HD6432351 Datasheet, PDF (784/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table A-5 Number of Cycles in Instruction Execution (cont)
Instruction
STC
STM
STMAC
SUB
SUBS
SUBX
TAS
TRAPA
XOR
XORC
Branch
Instruction Address
Fetch
Read
Stack Byte Data
Operation Access
Mnemonic
STC.B CCR,Rd
I
J
K
L
1
STC.B EXR,Rd
1
STC.W CCR,@ERd
2
STC.W EXR,@ERd
2
STC.W CCR,@(d:16,ERd)
3
STC.W EXR,@(d:16,ERd)
3
STC.W CCR,@(d:32,ERd)
5
STC.W EXR,@(d:32,ERd)
5
STC.W CCR,@-ERd
2
STC.W EXR,@-ERd
2
STC.W CCR,@aa:16
3
STC.W EXR,@aa:16
3
STC.W CCR,@aa:32
4
STC.W EXR,@aa:32
4
STM.L (ERn-ERn+1),@-SP
2
4
STM.L (ERn-ERn+2),@-SP
2
6
STM.L (ERn-ERn+3),@-SP
2
8
STMAC MACH,ERd
Cannot be used in the H8S/2350 Series
STMAC MACL,ERd
SUB.B Rs,Rd
1
SUB.W #xx:16,Rd
2
SUB.W Rs,Rd
1
SUB.L #xx:32,ERd
3
SUB.L ERs,ERd
1
SUBS #1/2/4,ERd
1
SUBX #xx:8,Rd
1
SUBX Rs,Rd
1
TAS @ERd
TRAPA #x:2
2
Normal
2
Advanced 2
2
1
2 / 3 *¹
2
2 / 3 *¹
XOR.B #xx:8,Rd
1
XOR.B Rs,Rd
1
XOR.W #xx:16,Rd
2
XOR.W Rs,Rd
1
XOR.L #xx:32,ERd
3
XOR.L ERs,ERd
2
XORC #xx:8,CCR
1
XORC #xx:8,EXR
2
Word Data Internal
Access Operation
M
N
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
Notes: 1. 2 when EXR is invalid, 3 when EXR is valid.
2. When n bytes of data are transferred.
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