HD6432351 Datasheet, PDF (8/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

2.9 Basic Timing...................................................................................................................... 65
2.9.1 Overview............................................................................................................... 65
2.9.2 On-Chip Memory (ROM, RAM).......................................................................... 65
2.9.3 On-Chip Supporting Module Access Timing ....................................................... 67
2.9.4 External Address Space Access Timing ............................................................... 68
Section 3 MCU Operating Modes................................................................................. 69
3.1 Overview............................................................................................................................ 69
3.1.1 H8S/2350 Operating Mode Selection ................................................................... 69
3.1.2 H8S/2351 Operating Mode Selection ................................................................... 70
3.1.3 Register Configuration.......................................................................................... 71
3.2 Register Descriptions ......................................................................................................... 71
3.2.1 Mode Control Register (MDCR) .......................................................................... 71
3.2.2 System Control Register (SYSCR)....................................................................... 72
3.3 Operating Mode Descriptions ............................................................................................ 73
3.3.1 Mode 1 .................................................................................................................. 73
3.3.2 Mode 2 (H8S/2351 Only) ..................................................................................... 73
3.3.3 Mode 3 (H8S/2351 Only) ..................................................................................... 73
3.3.4 Mode 4 .................................................................................................................. 73
3.3.5 Mode 5 .................................................................................................................. 74
3.3.6 Mode 6 (H8S/2351 Only) ..................................................................................... 74
3.3.7 Mode 7 (H8S/2351 Only) ..................................................................................... 74
3.4 Pin Functions in Each Operating Mode ............................................................................. 75
3.5 Memory Map in Each Operating Mode ............................................................................. 75
Section 4 Exception Handling........................................................................................ 79
4.1 Overview............................................................................................................................ 79
4.1.1 Exception Handling Types and Priority................................................................ 79
4.1.2 Exception Handling Operation ............................................................................. 80
4.1.3 Exception Vector Table ........................................................................................ 80
4.2 Reset................................................................................................................................... 82
4.2.1 Overview............................................................................................................... 82
4.2.2 Reset Types........................................................................................................... 82
4.2.3 Reset Sequence ..................................................................................................... 83
4.2.4 Interrupts after Reset............................................................................................. 84
4.2.5 State of On-Chip Supporting Modules after Reset Release.................................. 84
4.3 Traces ................................................................................................................................. 85
4.4 Interrupts ............................................................................................................................ 86
4.5 Trap Instruction.................................................................................................................. 87
4.6 Stack Status after Exception Handling .............................................................................. 88
4.7 Notes on Use of the Stack.................................................................................................. 89
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