HD6432351 Datasheet, PDF (163/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 6-3 Bus Specifications for Each Area (Basic Bus Interface)
ABWCR
ABWn
0
ASTCR
ASTn
0
1
1
0
1
WCRH, WCRL
Wn1
—
0
1
—
0
1
Wn0
—
0
1
0
1
—
0
1
0
1
Bus Specifications (Basic Bus Interface)
Bus Width
Program Wait
Access States States
16
2
0
3
0
1
2
3
8
2
0
3
0
1
2
3
6.3.3 Memory Interfaces
The H8S/2350 Series memory interfaces comprise a basic bus interface that allows direct
connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of
DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can
be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, and an area for which the
burst ROM interface is designated functions as burst ROM space.
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