HD6432351 Datasheet, PDF (706/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

21.3.1 Clock Timing
Table 21-4 lists the clock timing
Table 21-4 Clock Timing
Condition A: V_CC = 2.7 to 5.5 V, AV_CC = 2.7 to 5.5 V, V_ref = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Clock oscillator setting
time at reset (crystal)
Clock oscillator setting time
in software standby (crystal)
External clock output
stabilization delay time
Condition A Condition B
Symbol Min Max Min Max Unit
t _cyc
t _CH
t _CL
t _Cr
t _Cf
t _OSC1
100 500 50
35 — 20
35 — 20
— 15 —
— 15 —
20 — 10
500 ns
— ns
— ns
5
ns
5
ns
— ms
t _OSC2
20 — 10 — ms
t _DEXT
500 — 500 — µs
Test Conditions
Figure 21-4
Figure 21-4
Figure 21-5
Figure 20-2
Figure 21-5
t_cyc
t_CH
t_Cf
ø
t_CL
t_Cr
Figure 21-4 System Clock Timing
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