HD6432351 Datasheet, PDF (267/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in
DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.
Figure 7-13 illustrates operation in block transfer mode when MARB is designated as a block area.
Address T_A
1st block
2nd block
Transfer
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Block area
Address T_B
Address B_B
Address B_A
Nth block
Legend
Address TA = LA
Address TB = LB
Address BA = LA + SAIDE • (–1)^SAID • (2^DTSZ • (M•N–1))
Address BB = LB + DAIDE • (–1)^DAID • (2^DTSZ • (N–1))
Where : LA = Value set in MARA
LB = Value set in MARB
N = Value set in ETCRB
M = Value set in ETCRAH and ETCRAL
Figure 7-13 Operation in Block Transfer Mode (BLKDIR = 0)
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