HD6432351 Datasheet, PDF (319/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

DTC vector
address
Register information
start address
Register information
Chain transfer
Figure 8-4 Correspondence between DTC Vector Address and Register Information
8.3.4 Location of Register Information in Address Space
Figure 8-5 shows how the register information should be located in the address space.
Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address
of the register information (contents of the vector address). In the case of chain transfer, register
information should be located in consecutive areas.
Locate the register information in the on-chip RAM (addresses: H'FFF800 to H'FFFBFF).
Register
information
start address
Chain
transfer
Lower address
0
1
2
3
MRA
SAR
MRB
DAR
CRA
CRB
MRA
SAR
MRB
DAR
CRA
CRB
4 bytes
Register information
Register information
for 2nd transfer in
chain transfer
Figure 8-5 Location of Register Information in Address Space
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