HD6432351 Datasheet, PDF (774/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

A.4 Number of States Required for Instruction Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and
other cycles occurring in each instruction. Table A-4 indicates the number of states required for
each cycle. The number of states required for execution of an instruction can be calculated from
these two tables as follows:
Execution states = I × S_I + J × S_J + K × S_K + L ×S_L + M × S_M + N × S_N
Examples: Advanced mode, program code and stack located in external memory, on-chip
supporting modules accessed in two states with 8-bit bus width, external devices accessed in three
states with one wait state and 16-bit bus width.
1. BSET #0, @FFFFC7:8
From table A-5:
I = L = 2, J = K = M = N = 0
From table A-4:
S_I = 4, S_L = 2
Number of states required for execution = 2 × 4 + 2 × 2 = 12
2. JSR @@30
From table A-5:
I = J = K = 2, L = M = N = 0
From table A-4:
S_I = S_J = S_K = 4
Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24
754