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| HD6432351 Datasheet, PDF (230/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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Bit 1âData Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B
transfer end interrupt.
Bit 1
DTIE0B
0
1
Description
Transfer end interrupt disabled
Transfer end interrupt enabled
(Initial value)
Bit 0âData Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A
transfer end interrupt.
Bit 0
DTIE0A
0
1
Description
Transfer end interrupt disabled
Transfer end interrupt enabled
(Initial value)
210
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