HD6432351 Datasheet, PDF (298/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

7.7 Usage Notes
DMAC Register Access during Operation: Except for forced termination, the operating
(including transfer waiting state) channel setting should not be changed. The operating channel
setting should only be changed when transfer is disabled.
Also, the DMAC register should not be written to in a DMA transfer.
Module Stop: When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the
module stop state is entered. However, 1 cannot be written to the MSTP15 bit if any of the
DMAC channels is enabled. This setting should therefore be made when DMAC operation is
stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
• Transfer end/suspend interrupt (DTE = 0 and DTIE = 1)
• TEND pin enable (TEE = 1)
• DACK pin enable (FAE = 0 and SAE = 1)
Medium-Speed Mode: When the DTA bit is 0, internal interrupt signals specified as DMAC
transfer sources are edge-detected.
In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting
modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt
source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is
generated, is less than one state with respect to the DMAC clock (bus master clock), edge
detection may not be possible and the interrupt may be ignored.
Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the medium-
speed clock.
278