HD6432351 Datasheet, PDF (556/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

13.2.5 Serial Mode Register (SMR)
Bit
:
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E STOP
MP
CKS1 CKS0
Initial value :
0
0
0
0
0
0
0
0
R/W
:
R/W
R/W R/W
R/W R/W
R/W
R/W R/W
SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate
generator clock source.
SMR can be read or written to by the CPU at all times.
SMR is initialized to H'00 by a reset, and in standby mode or module stop mode.
Bit 7—Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode
as the SCI operating mode.
Bit 7
C/A
0
1
Description
Asynchronous mode
Clocked synchronous mode
(Initial value)
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR
Description
0
8-bit data
(Initial value)
1
7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible
to choose between LSB-first or MSB-first transfer.
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