HD6432351 Datasheet, PDF (896/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

RDR0—Receive Data Register 0
Bit
:
7
6
5
Initial value :
0
0
0
Read/Write :
R
R
R
H'FF7D SCI0, Smart Card Interface 0
4
3
2
1
0
0
0
0
0
0
R
R
R
R
R
Stores received serial data
SCMR0—Smart Card Mode Register 0
H'FF7E SCI0, Smart Card Interface 0
Bit
:
7
—
Initial value :
1
Read/Write : —
6
5
—
—
1
1
—
—
4
3
2
—
SDIR SINV
1
0
0
—
R/W R/W
1
0
—
SMIF
1
0
—
R/W
Smart Card
Interface Mode Select
0 Smart Card interface
function is disabled
1 Smart Card interface
function is enabled
Smart Card Data Invert
0 TDR contents are transmitted as they are
Receive data is stored in RDR as it is
1 TDR contents are inverted before
being transmitted
Receive data is stored in RDR
in inverted form
Smart Card Data Direction
0 TDR contents are transmitted LSB-first
Receive data is stored in RDR LSB-first
1 _{TDR contents are transmitted MSB-first}
Receive data is stored in RDR MSB-first
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