HD6432351 Datasheet, PDF (412/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

9.14.2 Register Configuration
Table 9-25 shows the port G register configuration.
Table 9-25 Port G Registers
Name
Abbreviation
R/W
Port G data direction register
PGDDR
W
Port G data register
PGDR
R/W
Port G register
PORTG
R
Notes: 1. Lower 16 bits of the address.
2. Value of bits 4 to 0.
3. Initial value depends on the mode.
Initial Value*²
H'10/H'00*³
H'00
Undefined
Address*¹
H'FEBF
H'FF6F
H'FF5F
Port G Data Direction Register (PGDDR)
Bit
:
7
6
5
4
3
2
1
0
—
—
— PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
Modes 1, 4, 5
Initial value : Undefined Undefined Undefined 1
0
0
0
0
R/W
:
—
—
—
W
W
W
W
W
Modes 2, 3, 6, 7
Initial value : Undefined Undefined Undefined 0
0
0
0
0
R/W
:
—
—
—
W
W
W
W
W
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an
undefined value will be read.
The PG4DDR bit is initialized by a power-on reset and in hardware standby mode, to 1 in modes
1, 4, and 5, and to 0 in modes 2, 3, 6, and 7. It retains its prior state after a manual reset and in
software standby mode. The OPE bit in SBYCR is used to select whether the bus control output
pins retain their output state or become high-impedance when a transition is made to software
standby mode.
• Mode 1 [H8S/2350]; modes 1 and 2 [H8S/2351]
Pin PG₄ functions as a bus control output pin (CS0) when the corresponding PGDDR bit is set
to 1, and as an input port when the bit is cleared to 0.
For pins PG₃ to PG₀, setting the corresponding PGDDR bit to 1 makes the pin an output port,
while clearing the bit to 0 makes the pin an input port.
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