HD6432351 Datasheet, PDF (866/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

DTVECR—DTC Vector Register
H'FF37
DTC
Bit
:7
6
5
4
3
2
1
0
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
Initial value : 0
0
0
0
0
0
0
0
Read/Write : R/(W)* R/W
R/W
R/W
R/W
R/W
R/W
R/W
Sets vector number for DTC software activation
DTC Software Activation Enable
0 DTC software activation is disabled
[Clearing condition]
When the DISEL bit is 0 and the specified number of transfers have
not ended
1 DTC software activation is enabled
[Holding conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
• During data transfer due to software activation
Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1
is read.
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