HD6432351 Datasheet, PDF (183/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.5.7 Precharge State Control
When DRAM is accessed, RAS precharging time must be secured. With the H8S/2350 Series, one
T_p state is always inserted when DRAM space is accessed. This can be changed to two T_p states by
setting the TPC bit in MCR to 1. Set the appropriate number of T_p cycles according to the DRAM
connected and the operating frequency of the H8S/2350 Series. Figure 6-16 shows the timing
when two T_p states are inserted.
When the TCP bit is set to 1, two T_p states are also used for refresh cycles.
T_p1
T_p2
T_r
T_c1
T_c2
ø
A₂₃ to A₀
row
column
CSn (RAS)
Read
Write
CAS, LCAS
HWR, LWR
(UWE, LWE)
D₁₅ to D₀
HWR, LWR
(UWE, LWE)
D₁₅ to D₀
Note: n = 2 to 5
Figure 6-16 Timing with Two Precharge States (2-WE System)
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