HD6432351 Datasheet, PDF (337/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 9-1 Port Functions (cont)
Port Description Pins
Mode 1 Mode 2*¹ Mode 3*¹ Mode 4 Mode 5 Mode 6*¹ Mode 7*¹
Port D • 8-bit I/O
port*¹
PD₇/D₁₅ to
PD₀/D₈
• Built-in
MOS input
pull-up*¹
Data bus input/
output
I/O port Data bus input/output
I/O port
Port E • 8-bit I/O
port
PE₇/D₇ to
PE₀/D₀
• Built-in
MOS input
pull-up*¹
In 8-bit bus mode: I/O port
I/O port
In 16-bit bus mode:
data bus input/output
In 8-bit bus mode: I/O port
In 16-bit bus mode: data bus
input/output
I/O port
Port F • 8-bit I/O
port
PF₇/ø
When DDR = 0:
When When DDR = 0: input port
input port
DDR = 0 _{When DDR = 1 (after reset):}
When DDR = 1 (after ^(after
ø output
reset):
reset):
ø output
input port
When
DDR = 1:
ø output
When
DDR = 0
(after
reset):
input port
When
DDR = 1:
ø output
PF₆/AS
PF₅/RD
PF₄/HWR
PF₃/LWR
PF₂/LCAS/
WAIT/
BREQO
AS, RD, HWR, LWR I/O port
output
When WAITE = 0 I/O port
and BREQOE = 0
(after reset): I/O port
AS, RD, HWR, LWR output
I/O port
When WAITE = 0 and
BREQOE = 0 (after reset): I/O
port
I/O port
When WAITE = 1
and BREQOE = 0:
WAIT input
When WAITE = 0
and BREQOE = 1:
BREQO input
When WAITE = 1: and
BREQOE = 0: WAIT input
When WAITE = 0 and
BREQOE = 1: BREQO output
When RMTS2 to RMTS0 =
B'001 to B'011, CW2 = 0, and
LCASS = 0: LCAS output
PF₁/BACK
PF₀/BREQ
When BRLE = 0
(after reset): I/O port
When BRLE = 1:
BREQ input, BACK
output
When BRLE = 0 (after reset):
I/O port
When BRLE = 1: BREQ input,
BACK output
Note: 1. Only applies to the H8S/2351.
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