HD6432351 Datasheet, PDF (149/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of
program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set
to 1.
Bit 3
W11
0
1
Bit 2
W10
0
1
0
1
Description
Program wait not inserted when external space area 1 is accessed
1 program wait state inserted when external space area 1 is accessed
2 program wait states inserted when external space area 1 is accessed
3 program wait states inserted when external space area 1 is accessed
(Initial value)
Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of
program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set
to 1.
Bit 1
W01
0
1
Bit 0
W00
0
1
0
1
Description
Program wait not inserted when external space area 0 is accessed
1 program wait state inserted when external space area 0 is accessed
2 program wait states inserted when external space area 0 is accessed
3 program wait states inserted when external space area 0 is accessed
(Initial value)
129