HD6432351 Datasheet, PDF (126/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

(2) 8-Level Control
In interrupt control mode 2, 8-level mask level determination is performed for the selected
interrupts in interrupt acceptance control according to the interrupt priority level (IPR).
The interrupt source selected is the interrupt with the highest priority level, and whose priority
level set in IPR is higher than the mask level.
Table 5-7 Interrupts Selected in Each Interrupt Control Mode (2)
Interrupt Control Mode
0
2
Selected Interrupts
All interrupts
Highest-priority-level (IPR) interrupt whose priority level is greater
than the mask level (IPR > I2 to I0).
(3) Default Priority Determination
When an interrupt is selected by 8-level control, its priority is determined and a vector number is
generated.
If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5-8 shows operations and control signal functions in each interrupt control mode.
Table 5-8 Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt
Control ^Setting
Mode INTM1 INTM0
Interrupt
Acceptance Control
I
Default
8-Level Control _Priority
T
I2 to I0 IPR Determination (Trace)
0
0
0
IM
X—
—*²
—
2
1
0
X —*¹
IM
PR
T
Legend
: Interrupt operation control performed
X : No operation. (All interrupts enabled)
IM : Used as interrupt mask bit
PR : Sets priority.
— : Not used.
*¹ : Set to 1 when interrupt is accepted.
*² : Keep the initial setting.
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