HD6432351 Datasheet, PDF (656/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 15-4 A/D Conversion Time (Single Mode)
CKS = 0
Item
Symbol
Min Typ Max Min
A/D conversion start delay
t_D
10 —
Input sampling time
t _SPL
— 63
A/D conversion time
t _CONV
259 —
Note: Values in the table are the number of states.
17 6
——
266 131
CKS = 1
Typ Max
—9
31 —
— 134
15.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit has been set to 1 by software. Figure 15-6 shows the
timing.
ø
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 15-6 External Trigger Input Timing
636