HD6432351 Datasheet, PDF (602/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Serial clock
Transfer direction
Serial data
Bit 7 Bit 0
Bit 7 Bit 0 Bit 1
Bit 6 Bit 7
TDRE
TEND
TXI interrupt
Data written to TDR
request generated and TDRE flag
cleared to 0 in TXI
interrupt service routine
TXI interrupt
request generated
TEI interrupt
request generated
1 frame
Figure 13-17 Example of SCI Operation in Transmission
• Serial data reception (clocked synchronous mode)
Figure 13-18 shows a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
When changing the operating mode from asynchronous to clocked synchronous, be sure to
check that the ORER, PER, and FER flags are all cleared to 0.
The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor
receive operations will be possible.
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