HD6432351 Datasheet, PDF (623/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

14.3.3 Data Format
Figure 14-3 shows the Smart Card interface data format. In reception in this mode, a parity check
is carried out on each frame, and if an error is detected an error signal is sent back to the
transmitting end, and retransmission of the data is requested. If an error signal is sampled during
transmission, the same data is retransmitted.
When there is no parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transmitting station output
When a parity error occurs
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Legend
Ds
: Start bit
D0 to D7 : Data bits
Dp
: Parity bit
DE
: Error signal
Transmitting station output
Receiving station
output
Figure 14-3 Smart Card Interface Data Format
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