HD6432351 Datasheet, PDF (194/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.6 DMAC Single Address Mode and DRAM Interface
When burst mode is selected with the DRAM interface, the DACK output timing can be selected
with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same
time, whether or not burst access is to be performed is selected.
6.6.1 When DDS = 1
Burst access is performed by determining the address only, irrespective of the bus master. The
DACK output goes low from the T_C1 state in the case of the DRAM interface.
Figure 6-28 shows the DACK output timing for the DRAM interface when DDS = 1.
ø
A₂₃ to A₀
CSn (RAS)
CAS, (UCAS)
LCAS (LCAS)
Read
HWR, (WE)
D₁₅ to D₀
Write
HWR, (WE)
D₁₅ to D₀
DACK
T_p
T_r
T_c1
T_c2
Row
Column
Figure 6-28 DACK Output Timing when DDS = 1 (Example of DRAM Access)
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