HD6432351 Datasheet, PDF (885/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

PGDR—Port G Data Register
H'FF6F
Port G
Bit
:
7
6
5
4
—
—
— PG4DR
Initial value : _{Undefined Undefined Undefined 0}
Read/Write : _—
—
—
R/W
3
PG3DR
0
R/W
2
PG2DR
0
R/W
1
PG1DR
0
R/W
0
PG0DR
0
R/W
Stores output data for port G pins (PG₄ to PG₀)
PAPCR—Port A MOS Pull-Up Control Register H'FF70
Port A
[H8S/2351 Only]
Bit
:
7
6
5
4
3
2
1
0
PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR
Initial value :
0
0
0
0
0
0
0
0
Read/Write : R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis
PBPCR—Port B MOS Pull-Up Control Register H'FF71
Port B
[H8S/2351 Only]
Bit
:
7
6
5
4
3
2
1
0
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR
Initial value :
0
0
0
0
0
0
0
0
Read/Write : R/W
R/W R/W
R/W R/W R/W
R/W R/W
Controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis
865