HD6432351 Datasheet, PDF (779/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table A-5 Number of Cycles in Instruction Execution (cont)
Instruction
BSR
BST
BTST
BXOR
CLRMAC
CMP
DAA
DAS
DEC
DIVXS
DIVXU
Branch
Instruction Address
Fetch
Read
Stack Byte Data
Operation Access
Mnemonic
BSR d:8
I
Normal
2
J
K
L
1
Advanced 2
2
BSR d:16
Normal
2
1
Advanced 2
2
BST #xx:3,Rd
1
BST #xx:3,@ERd
2
2
BST #xx:3,@aa:8
2
2
BST #xx:3,@aa:16
3
2
BST #xx:3,@aa:32
4
2
BTST #xx:3,Rd
1
BTST #xx:3,@ERd
2
1
BTST #xx:3,@aa:8
2
1
BTST #xx:3,@aa:16
3
1
BTST #xx:3,@aa:32
4
1
BTST Rn,Rd
1
BTST Rn,@ERd
2
1
BTST Rn,@aa:8
2
1
BTST Rn,@aa:16
3
1
BTST Rn,@aa:32
4
1
BXOR #xx:3,Rd
1
BXOR #xx:3,@ERd
2
1
BXOR #xx:3,@aa:8
2
1
BXOR #xx:3,@aa:16
3
1
BXOR #xx:3,@aa:32
4
1
CLRMAC
Cannot be used in the H8S/2350 Series
CMP.B #xx:8,Rd
1
CMP.B Rs,Rd
1
CMP.W #xx:16,Rd
2
CMP.W Rs,Rd
1
CMP.L #xx:32,ERd
3
CMP.L ERs,ERd
1
DAA Rd
1
DAS Rd
1
DEC.B Rd
1
DEC.W #1/2,Rd
1
DEC.L #1/2,ERd
1
DIVXS.B Rs,Rd
2
DIVXS.W Rs,ERd
2
DIVXU.B Rs,Rd
1
DIVXU.W Rs,ERd
1
Word Data Internal
Access Operation
M
N
1
1
11
19
11
19
759