HD6432351 Datasheet, PDF (503/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 10-53 shows the timing in this case.
ø
Address
Read signal
Input capture
signal
TGR
Internal
data bus
TGR read cycle
T1
T2
TGR address
X
M
M
Figure 10-53 Contention between TGR Read and Input Capture
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