HD6432351 Datasheet, PDF (372/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

9.7.2 Register Configuration
Table 9-11 shows the port 6 register configuration.
Table 9-11 Port 6 Registers
Name
Abbreviation
R/W
Port 6 data direction register
P6DDR
W
Port 6 data register
P6DR
R/W
Port 6 register
PORT6
R
Note: * Lower 16 bits of the address.
Initial Value
H'00
H'00
Undefined
Address*
H'FEB5
H'FF65
H'FF55
Port 6 Data Direction Register (P6DDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read.
Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P6DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. As the DMAC is initialized by a
manual reset, the pin states are determined by the P6DDR and P6DR specifications.
Port 6 Data Register (P6DR)
Bit
:
Initial value :
R/W
:
7
P67DR
0
R/W
6
P66DR
0
R/W
5
P65DR
0
R/W
4
P64DR
0
R/W
3
P63DR
0
R/W
2
P62DR
0
R/W
1
P61DR
0
R/W
0
P60DR
0
R/W
P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P6₇ to P6₀).
P6DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
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