HD6432351 Datasheet, PDF (697/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Oscillator
RES
STBY
Oscillation
stabilization
time
Reset
exception
handling
Figure 20-3 Hardware Standby Mode Timing (Example)
20.8 ø Clock Output Disabling Function
Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle,
and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set.
Table 20-5 shows the state of the ø pin in each processing state.
Table 20-5 ø Pin State in Each Processing State
DDR
PSTOP
Hardware standby mode
Software standby mode
Sleep mode
Normal operating state
0
—
High impedance
High impedance
High impedance
High impedance
1
0
Fixed high
ø output
ø output
1
Fixed high
Fixed high
677