HD6432351 Datasheet, PDF (549/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Section 13 Serial Communication Interface (SCI)
13.1 Overview
The H8S/2350 Series is equipped with a two-channel serial communication interface (SCI). All
two channels have the same functions. The SCI can handle both asynchronous and clocked
synchronous serial communication. A function is also provided for serial communication between
processors (multiprocessor communication function).
13.1.1 Features
SCI features are listed below.
• Choice of asynchronous or clocked synchronous serial communication mode
Asynchronous mode
 Serial data communication executed using asynchronous system in which synchronization
is achieved character by character
 Serial data communication can be carried out with standard asynchronous communication
chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous
Communication Interface Adapter (ACIA)
 A multiprocessor communication function is provided that enables serial data
communication with a number of processors
 Choice of 12 serial data transfer formats
Data length
: 7 or 8 bits
Stop bit length
: 1 or 2 bits
Parity
: Even, odd, or none
Multiprocessor bit
: 1 or 0
 Receive error detection : Parity, overrun, and framing errors
 Break detection
: Break can be detected by reading the RxD pin level
directly in case of a framing error
Clocked Synchronous mode
 Serial data communication synchronized with a clock
 Serial data communication can be carried out with other chips that have a synchronous
communication function
 One serial data transfer format
 Data length
: 8 bits
 Receive error detection : Overrun errors detected
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