HD6432351 Datasheet, PDF (982/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Appendix E Pin States at Power-On
Note that pin states at power-on depend on the state of the STBY pin and NMI pin. The case in
which pins settle* from an indeterminate state at power-on, and the case in which pins settle* from
the high-impedance state, are described below.
After reset release, power-on reset exception handling is started.
Note: * “Settle” refers to the pin states in a power-on reset in each MCU operating mode.
E.1 When Pins Settle from an Indeterminate State at Power-On
When the NMI pin level changes from low to high after powering on, the chip goes to the power-
on reset state after a high level is detected at the NMI pin. While the chip detects a low level at the
NMI pin, the manual reset state is established. The pin states are indeterminate during this interval.
(Ports may output an internally determined value after powering on.)
The NMI setup time (t_NMIS) is necessary for the chip to detect a high level at the NMI pin.
V_CC
STBY
Manual reset
NMI
RES
φ
t_OSC1
Power-on reset
NMI = Low → NMI = High
RES = Low
Figure E-1 When Pins Settle from an Indeterminate State at Power-On
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