HD6432351 Datasheet, PDF (141/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.1.2 Block Diagram
Figure 6-1 shows a block diagram of the bus controller.
CS0 to CS7
Area decoder
External bus control signals
BREQ
BACK
BREQO
ABWCR
ASTCR
BCRH
BCRL
Bus
controller
Internal
address bus
Internal control
signals
Bus mode signal
WAIT
Wait
controller
WCRH
WCRL
External DRAM
signals
DRAM/PSRAM
controller
MCR
DRAMCR
RTCNT
RTCOR
Bus arbiter
CPU bus request signal
DTC bus request signal
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
Figure 6-1 Block Diagram of Bus Controller
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