HD6432351 Datasheet, PDF (22/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 1-1 Overview
Item
CPU
Bus controller
DMA controller
(DMAC)
Specification
• General-register machine
 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
• High-speed operation suitable for realtime control
 Maximum clock rate: 20 MHz
 High-speed arithmetic operations
8/16/32-bit register-register add/subtract : 50 ns
16 × 16-bit register-register multiply
: 1000 ns
32 ÷ 16-bit register-register divide
: 1000 ns
• Instruction set suitable for high-speed operation
 Sixty-five basic instructions
 8/16/32-bit move/arithmetic and logic instructions
 Unsigned/signed multiply and divide instructions
 Powerful bit-manipulation instructions
• Two CPU operating modes
 Normal mode
: 64-kbyte address space
 Advanced mode : 16-Mbyte address space
• Address space divided into 8 areas, with bus specifications settable
independently for each area
• Chip select output possible for each area
• Choice of 8-bit or 16-bit access space for each area
• 2-state or 3-state access space can be designated for each area
• Number of program wait states can be set for each area
• Burst ROM directly connectable
• Maximum 8-Mbyte DRAM directly connectable (or use of interval timer
possible)
• External bus release function
• Choice of short address mode or full address mode
• 4 channels in short address mode
• 2 channels in full address mode
• Transfer possible in repeat mode, block transfer mode, etc.
• Single address mode transfer possible
• Can be activated by internal interrupt
2