HD6432351 Datasheet, PDF (192/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

ø
RTCNT
N
H'00
RTCOR
N
Refresh request signal
and CMF bit setting signal
Figure 6-24 Compare Match Timing
T_Rp
T_Rr
T_Rc1
T_Rc2
ø
CS (RAS)
CAS, LCAS
Figure 6-25 CBR Refresh Timing
When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS
signal should be adjusted with bits RLW1 and RLW0. These bits are only enabled in refresh
operations.
Figure 6-26 shows the timing when the RCW bit is set to 1.
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