HD6432351 Datasheet, PDF (536/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

12.1.2 Block Diagram
Figure 12-1 shows a block diagram of the WDT.
WOVI
(interrupt request
signal)
WDTOVF
Internal reset signal*
Interrupt
control
Reset
control
Overflow
Clock
Clock
select
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
Internal clock
sources
RSTCSR
TCNT
TSCR
Module bus
Bus
interface
WDT
Legend
TCSR : Timer control/status register
TCNT : Timer counter
RSTCSR : Reset control/status register
Note: * The type of internal reset signal depends on a register setting. Either power-on reset or manual
reset can be selected.
Figure 12-1 Block Diagram of WDT
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