HD6432351 Datasheet, PDF (17/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Section 14 Smart Card Interface ...................................................................................... 593
14.1 Overview............................................................................................................................ 593
14.1.1 Features ................................................................................................................. 593
14.1.2 Block Diagram...................................................................................................... 594
14.1.3 Pin Configuration.................................................................................................. 595
14.1.4 Register Configuration.......................................................................................... 596
14.2 Register Descriptions ......................................................................................................... 597
14.2.1 Smart Card Mode Register (SCMR)..................................................................... 597
14.2.2 Serial Status Register (SSR) ................................................................................. 598
14.2.3 Serial Mode Register (SMR) ................................................................................ 599
14.2.4 Serial Control Register (SCR) .............................................................................. 600
14.3 Operation............................................................................................................................ 601
14.3.1 Overview............................................................................................................... 601
14.3.2 Pin Connections .................................................................................................... 602
14.3.3 Data Format .......................................................................................................... 603
14.3.4 Register Settings ................................................................................................... 605
14.3.5 Clock ..................................................................................................................... 607
14.3.6 Data Transfer Operations...................................................................................... 609
14.3.7 Operation in GSM Mode ...................................................................................... 616
14.4 Usage Notes ....................................................................................................................... 617
Section 15 A/D Converter.................................................................................................. 621
15.1 Overview............................................................................................................................ 621
15.1.1 Features ................................................................................................................. 621
15.1.2 Block Diagram...................................................................................................... 622
15.1.3 Pin Configuration.................................................................................................. 623
15.1.4 Register Configuration.......................................................................................... 624
15.2 Register Descriptions ......................................................................................................... 625
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 625
15.2.2 A/D Control/Status Register (ADCSR) ................................................................ 626
15.2.3 A/D Control Register (ADCR) ............................................................................. 628
15.2.4 Module Stop Control Register (MSTPCR)........................................................... 629
15.3 Interface to Bus Master...................................................................................................... 630
15.4 Operation............................................................................................................................ 631
15.4.1 Single Mode (SCAN = 0) ..................................................................................... 631
15.4.2 Scan Mode (SCAN = 1)........................................................................................ 633
15.4.3 Input Sampling and A/D Conversion Time .......................................................... 635
15.4.4 External Trigger Input Timing.............................................................................. 636
15.5 Interrupts ............................................................................................................................ 637
15.6 Usage Notes ....................................................................................................................... 637
Section 16 D/A Converter.................................................................................................. 643
16.1 Overview............................................................................................................................ 643
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